Specification-driven Compact Test Suite Generation for Complex Processor Pipelines
| dc.contributor.author | NGA, Dang T. Thanh | en_US |
| dc.contributor.author | ROYCHOUDHURY, Abhik | en_US |
| dc.contributor.author | MITRA, Tulika | en_US |
| dc.date.accessioned | 2007-12-03T09:10:34Z | en_US |
| dc.date.accessioned | 2017-01-23T07:00:30Z | |
| dc.date.available | 2007-12-03T09:10:34Z | en_US |
| dc.date.available | 2017-01-23T07:00:30Z | |
| dc.date.issued | 2007-11-21 | en_US |
| dc.description.abstract | Testing of modern-day processors to achieve gate-level coverage is a complex activity. While VLSI testing methods are extremely useful, they are unaware of the micro-architectural features of the processor. Functional validation of a processor design through simulation of a suite of test programs is a common industrial practice. In this paper, we develop a high-level architectural specification driven methodology for systematic test suite generation. Our primary contributions are (1) a fully formal processor pipeline modeling framework based on Communicating Extended Finite State Machines and (2) on-the-fly exploration of the processor model to generate test program witnesses, with an aim to achieve complete state coverage. While we achieve 100% coverage, random test generation manages to cover as low as 10% of the state space with comparable sized test suite. Moreover, we achieve significant reduction in the test-suite size compared to previously studied formal approaches that rely on querying an external model checker for test generation. | en_US |
| dc.format.extent | 367142 bytes | en_US |
| dc.format.mimetype | application/pdf | en_US |
| dc.identifier.uri | https://dl.comp.nus.edu.sg/xmlui/handle/1900.100/2614 | en_US |
| dc.language.iso | en | en_US |
| dc.relation.ispartofseries | TR21/07 | en_US |
| dc.title | Specification-driven Compact Test Suite Generation for Complex Processor Pipelines | en_US |
| dc.type | Technical Report | en_US |