Specification-driven Compact Test Suite Generation for Complex Processor Pipelines
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Date
2007-11-21
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Abstract
Testing of modern-day processors to achieve gate-level coverage is a complex activity. While VLSI testing methods are extremely useful, they are unaware of the micro-architectural features of the processor. Functional validation of a processor design through simulation of a suite of test programs is a common industrial practice. In this paper, we develop a high-level architectural specification driven methodology for systematic test suite generation. Our primary contributions are (1) a fully formal processor pipeline modeling framework based on Communicating Extended Finite State Machines and (2) on-the-fly exploration of the processor model to generate test program witnesses, with an aim to achieve complete state coverage. While we achieve 100% coverage, random test generation manages to cover as low as 10% of the state space with comparable sized test suite. Moreover, we achieve significant reduction in the test-suite size compared to previously studied formal approaches that rely on querying an external model checker for test generation.