Improved Algorithms for Low Power Multiplexor Decomposition
| dc.contributor.author | YANG, Shaofa | en_US |
| dc.contributor.author | LEONG, Hon Wai | en_US |
| dc.date.accessioned | 2006-05-17T09:04:24Z | en_US |
| dc.date.accessioned | 2017-01-23T06:59:59Z | |
| dc.date.available | 2006-05-17T09:04:24Z | en_US |
| dc.date.available | 2017-01-23T06:59:59Z | |
| dc.date.issued | 2006-05-17T09:04:24Z | en_US |
| dc.description.abstract | It has been estimated that multiplexors (MUXes) make up a major portion of the circuitry in a typical chip. Therefore, to reduce power consumption of a chip, it is important to consider the design of MUXes that consumes less power. This is called the low power MUX decomposition problem and has been studied in [NLCL97]. This paper improves on the results of [NLCL97] in two ways: (a) we propose a method to speed up the algorithms in [NLCL97], and (b) we propose a post-optimization procedure to further reduce the overall power dissipation of decompositions obtained by any MUX decomposition algorithm. Using this post-optimization procedure, we have been able to further reduce the power dissipation results of [NLCL97]. [NLCL97] U. Narayanan, H.W. Leong, K.-S. Chung, and C.L. Liu, ``Low power multiplexer decomposition", in Proc. of Int. Symp. on Low Power Electronics and Design 1997, pp. 269--274, IEEE Press, 1997. | en_US |
| dc.format.extent | 495043 bytes | en_US |
| dc.format.mimetype | application/pdf | en_US |
| dc.identifier.uri | https://dl.comp.nus.edu.sg/xmlui/handle/1900.100/2211 | en_US |
| dc.language.iso | en | en_US |
| dc.relation.ispartofseries | TRC5/06 | en_US |
| dc.title | Improved Algorithms for Low Power Multiplexor Decomposition | en_US |
| dc.type | Technical Report | en_US |