Improved Algorithms for Low Power Multiplexor Decomposition
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2006-05-17T09:04:24Z
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Abstract
It has been estimated that multiplexors (MUXes) make up a major portion of the circuitry in a typical chip. Therefore, to reduce power consumption of a chip, it is important to consider the design of MUXes that consumes less power. This is called the low power MUX
decomposition problem and has been studied in [NLCL97]. This paper improves on the results of [NLCL97] in two ways: (a) we propose a method to speed up the algorithms in [NLCL97], and (b) we propose a post-optimization procedure to further reduce the overall power dissipation of decompositions obtained by any MUX decomposition algorithm. Using this post-optimization procedure, we have been able to further reduce the power dissipation results of [NLCL97].
[NLCL97] U. Narayanan, H.W. Leong, K.-S. Chung, and C.L. Liu, ``Low power multiplexer decomposition", in Proc. of Int. Symp. on Low Power Electronics and Design 1997, pp. 269--274, IEEE Press, 1997.