Browsing by Author "MITRA, Tulika"

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    Exploiting Forwarding to Improve Data Bandwidth of Instruction-Set Extensions
    (2006-05-04) JAYASEELAN, Ramkumar; LIU, Haibin; MITRA, Tulika
    Application-specific instruction-set extensions (custom instructions) help embedded processors achieve higher performance. Most custom instructions offering significant performance benefit require multiple input operands. Unfortunately, RISC style embedded processors are designed to support at most two input operands per instruction. This data bandwidth problem is due to the limited number of read ports in the register file per instruction as well as the fixed-length instruction encoding. We propose to overcome this restriction by exploiting the data forwarding feature present in processor pipelines. With minimal modifications to the pipeline and the instruction encoding along with cooperation from the compiler, we can supply up to two additional input operands per custom instruction. Experimental results indicate that our approach achieves 87--100% of the ideal performance limit for standard benchmark programs. Additionally our scheme can be used to avoid unnecessary access to the register file thus saving 25% of register file energy.
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    Modeling Out-of-Order Processors for WCET Analysis
    (2005-09-13T09:13:58Z) LI, Xianfeng; ROYCHOUDHURY, Abhik; MITRA, Tulika
    Estimating the Worst Case Execution Time (WCET) of a program on a given processor is important for the schedulability analysis of real-time systems. WCET analysis techniques typically model the timing effects of micro-architectural features in modern processors (such as the pipeline, cache, branch prediction, etc.) to obtain safe and tight estimates. In this paper, we model out-of-order processor pipelines for WCET analysis. The analysis is, in general, difficult even for a basic block (a sequence of instructions with single-entry and single-exit points) if some of the instructions have variable latencies. This is because the WCET of a basic block on out-of-order pipelines cannot be obtained by assuming maximum latencies of the individual instructions. Our timing estimation technique for a basic block proceeds by a fixed-point analysis of the time intervals at which the instructions enter/leave a pipeline stage. To extend our estimation to whole programs, we use Integer Linear Programming (ILP) to combine the timing estimates for basic blocks. Timing effects of instruction cache and branch prediction are also modeled within our pipeline analysis framework. This forms a combined timing analysis framework that captures out-of-order pipeline, cache, branch prediction as well as the mutual interaction among these micro-architectural features. The accuracy of our analysis is demonstrated via tight estimates obtained for several benchmarks.
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    Specification-driven Compact Test Suite Generation for Complex Processor Pipelines
    (2007-11-21) NGA, Dang T. Thanh; ROYCHOUDHURY, Abhik; MITRA, Tulika
    Testing of modern-day processors to achieve gate-level coverage is a complex activity. While VLSI testing methods are extremely useful, they are unaware of the micro-architectural features of the processor. Functional validation of a processor design through simulation of a suite of test programs is a common industrial practice. In this paper, we develop a high-level architectural specification driven methodology for systematic test suite generation. Our primary contributions are (1) a fully formal processor pipeline modeling framework based on Communicating Extended Finite State Machines and (2) on-the-fly exploration of the processor model to generate test program witnesses, with an aim to achieve complete state coverage. While we achieve 100% coverage, random test generation manages to cover as low as 10% of the state space with comparable sized test suite. Moreover, we achieve significant reduction in the test-suite size compared to previously studied formal approaches that rely on querying an external model checker for test generation.