Exploiting Forwarding to Improve Data Bandwidth of Instruction-Set Extensions
| dc.contributor.author | JAYASEELAN, Ramkumar | en_US |
| dc.contributor.author | LIU, Haibin | en_US |
| dc.contributor.author | MITRA, Tulika | en_US |
| dc.date.accessioned | 2006-06-14T06:39:30Z | en_US |
| dc.date.accessioned | 2017-01-23T06:59:59Z | |
| dc.date.available | 2006-06-14T06:39:30Z | en_US |
| dc.date.available | 2017-01-23T06:59:59Z | |
| dc.date.issued | 2006-05-04 | en_US |
| dc.description.abstract | Application-specific instruction-set extensions (custom instructions) help embedded processors achieve higher performance. Most custom instructions offering significant performance benefit require multiple input operands. Unfortunately, RISC style embedded processors are designed to support at most two input operands per instruction. This data bandwidth problem is due to the limited number of read ports in the register file per instruction as well as the fixed-length instruction encoding. We propose to overcome this restriction by exploiting the data forwarding feature present in processor pipelines. With minimal modifications to the pipeline and the instruction encoding along with cooperation from the compiler, we can supply up to two additional input operands per custom instruction. Experimental results indicate that our approach achieves 87--100% of the ideal performance limit for standard benchmark programs. Additionally our scheme can be used to avoid unnecessary access to the register file thus saving 25% of register file energy. | en_US |
| dc.format.extent | 574937 bytes | en_US |
| dc.format.mimetype | application/pdf | en_US |
| dc.identifier.uri | https://dl.comp.nus.edu.sg/xmlui/handle/1900.100/2213 | en_US |
| dc.language.iso | en | en_US |
| dc.relation.ispartofseries | TRB5/06 | en_US |
| dc.title | Exploiting Forwarding to Improve Data Bandwidth of Instruction-Set Extensions | en_US |
| dc.type | Technical Report | en_US |