Safety Proofs of Presistence Analysis

dc.contributor.authorHUYNH, Bach Khoaen_US
dc.contributor.authorJU, Leien_US
dc.contributor.authorROYCHOUDHURY, Abhiken_US
dc.date.accessioned2010-10-28T03:45:30Zen_US
dc.date.accessioned2017-01-23T07:00:13Z
dc.date.available2010-10-28T03:45:30Zen_US
dc.date.available2017-01-23T07:00:13Z
dc.date.issued2010-10-28T03:45:30Zen_US
dc.description.abstractCaches are widely used in modern computer systems to bridge the increasing gap between processor speed and memory access time. On the other hand, the presence of caches, especially data caches, complicates the static worst case execution time (WCET) analysis. Correctness and tightness of WCET estimates are of crucial importance for system level design of embedded systems. In this report, we show that the originally proposed persistence analysis is both unsafe and pessimistic for worst-case cache behavior modeling.We propose a new update and join functions for persistence analysis and prove their soundness. Furthermore, we extend the semantics of memory block persistence, and propose a scope-aware persistence analysis which combines access pattern analysis and abstract interpretation. The dynamic behavior of a memory access is captured by its temporal scope (the loop iterations where a given memory block is accessed for a given data reference) during address analysis. Temporal scopes as well as loop hierarchy structure (the static scopes) are integrated and utilized to achieve a more precise abstract cache state modeling. We also prove the correctness of the proposed new persistence analysis.en_US
dc.format.extent543262 bytesen_US
dc.format.mimetypeapplication/pdfen_US
dc.identifier.urihttps://dl.comp.nus.edu.sg/xmlui/handle/1900.100/3303en_US
dc.language.isoenen_US
dc.relation.ispartofseriesTR20/10en_US
dc.titleSafety Proofs of Presistence Analysisen_US
dc.typeTechnical Reporten_US
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