Browsing by Author "CHAKRABORTY, Samarjit"

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    A Mathematical Framework for Video Quality
    (2011-06-16) GANGADHARAN, Deepak; PHAN, Linh T.X.; CHAKRABORTY, Samarjit; ZIMMERMANN, Roger; LEE, Insup
    We study the impact of video frame drops in bufferconstrained multiprocessor system-on-chip (MPSoC) platforms. Since on-chip buffer memory occupies a significant amount of silicon area, accurate buffer sizing has attracted a lot of research interest lately. However, all previous work studied this problem with the underlying assumption that no video frame drops can be tolerated. In reality, multimedia applications can often tolerate some frame drops without significantly deteriorating their output quality. Although system simulations can be used to perform video quality driven buffer sizing, they are time consuming. In this paper, we first demonstrate a dual-buffer management scheme to drop only the less significant frames. Based on this scheme, we then propose a formal framework to evaluate the buffer size vs video quality trade-offs, which in turn will help a system designer to perform quality driven buffer sizing. In particular, we mathematically haracterize the maximum numbers of frame drops for various buffer sizes and evaluate how they affect the worst-case PSNR value of the decoded video. We evaluate our proposed framework with an MPEG-2 decoder and compare the obtained results with that of a cycle-accurate simulator. Our evaluations show that for an acceptable quality of 30 dB, it is possible to reduce the buffer size by upto 28.6% which amounts to 25.88 megabits.
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    Processor Frequency Selection in Energy-Aware SoC Platform Design for Multimedia Application
    (2004-11-18T06:34:11Z) LIU, Yahong; MAXIAGUINE, Alexander; CHAKRABORTY, Samarjit; OOI, Wei Tsang
    Of late, there has been a considerable interest in generic and configurable System-on-Chip platforms specifically targeted towards implementing multimedia applications. A number of such platforms offer the possibility of including processor soft cores which are highly customizable. For voltage/frequency scaled processors, such customization includes the selection of appropriate voltage/frequency operating points which are tuned to the application set to be mapped onto the platform. In this context, we present an analytical framework that can guide a system designer in identifying the frequency ranges that should be supported by the different processors of a platform architecture. This framework can also be used to identify how such frequency ranges depend on the different parameters of the architecture (such as on-chip buffer sizes), and the performance impacts associated with selecting a particular frequency range. In the case of multimedia streaming applications, identifying such performance impacts and tradeoffs involved in customizing a platform architecture is especially difficult due to the bursty nature of on-chip traffic arising out of multimedia processing and the high variability in their execution requirements. The framework presented here is designed to precisely capture such characteristics and can be used in the design-space exploration of energy-aware platform architectures for multimedia processing.
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    Schedulability Analysis of MSC-based System Models
    (2007-10-23T01:40:39Z) JU, Lei; ROYCHOUDHURY, Abhik; CHAKRABORTY, Samarjit
    Message Sequence Charts (MSCs) are widely used for describing interaction scenarios between the components of a distributed system. Consequently, worst-case response time estimation and schedulability analysis of MSC-based speci.-cations form natural building blocks for designing distributed real-time systems. However, currently there exists a large gap between the timing and quantitative performance analysis techniques that exist in the real-time systems literature, and the modeling/speci.cation techniques that are advocated by the formal methods community. As a result, although a number of schedulability analysis techniques are known for a variety of task graph-based models, it is not clear if they can be used to effectively analyze standard speci.cation formalisms such as MSCs. In this work, we make an attempt to bridge this gap by proposing a schedulability analysis technique for MSC-based system speci.cations. We show that compared to existing timing analysis techniques for distributed real-time systems, our pro-posed analysis gives tighter results, which immediately translate to better system design and improved resource dimensioning. We illustrate the details of our analy-sis using a setup from the automotive electronics domain, which consist of two real-life application programs (that are naturally modeled using MSCs) running on a platform consisting of multiple electronic control units (ECUs) connected via a FlexRay bus.