Technical Reports

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Browsing Technical Reports by Author "Abhik ROYCHOUDHURY"

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    Modeling Out-of-Order Processors for Software Timing Analysis
    (2004-08-01T00:00:00Z) Xianfeng LI; Abhik ROYCHOUDHURY; Tulika MITRA
    Estimating the Worst Case Execution Time (WCET) of a program on a given processor is important for the schedulability analysis of real-time systems. WCET analysis techniques typically model the timing effects of microarchitectural features in modern processors (such as the pipeline, caches, branch prediction, etc.) to obtain safe but tight estimates. In this paper, we model out-of-order processor pipelines for WCET analysis. This analysis is, in general, difficult even for a basic block (a sequence of instructions with single-entry and single-exit point) if some of the instructions have variable latencies. This is because the worst case execution time of a basic block on out-of-order pipelines cannot be obtained by assuming maximum latencies of the individual instructions. Our timing estimation technique for a basic block is inspired by an existing performance analysis technique for tasks with data dependences and resource contentions in real-time distributed systems. We extend our analysis by modeling the interaction among consecutive basic blocks as well as the effect of instruction cache. Finally, we employ Integer Linear Programming (ILP) to compute the WCET of an entire program. The accuracy of our analysis is demonstrated via tight estimates obtained for several benchmarks.
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    Performance Impact of Multithreaded Java Semantics on Multiprocessor Memory Consistency Models
    (2003-07-01T00:00:00Z) Lei XIE; Abhik ROYCHOUDHURY; Tulika MITRA
    The semantics of Java multithreading dictates all possible behaviors that a multithreaded Java program can exhibit on any platform. This is called the Java memory model and describes the allowed re-orderings among the operations in a thread. However, multiprocessor platforms traditionally have a memory consistency model of their own. Consequently memory barriers may have to be inserted to ensure that the multiprocessor execution of a multithreaded Java program respects the Java Memory Model. In this paper, we study the impact of these additional memory barriers on multiprocessor performance. We also study how different choices of the Java Memory Model a_ect multiprocessor performance. Our experimental results are obtained by simulating multithreaded Java Grande benchmarks under various software and hardware memory models.
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    Symbolic Simulation of Live Sequence Charts
    (2003-07-01T00:00:00Z) Shishir C. CHOUDHARY; Abhik ROYCHOUDHURY; Roland Hock Chuan YAP
    Message Sequence Charts (MSC) have traditionally been used as a weak form of requirements specification in software design; they denote scenarios which may happen. Live Sequence Charts (LSC)extend Message Sequence Charts by also allowing the designer to specify scenarios which must happen. Live Sequence Chart specifications are executable; their simulation allows the designer to play out potentially aberrant scenarios prior to software construction. In this paper, we develop a simulation engine for Live Sequence Charts using CLP technology. The utility of (constraint) logic programming in this application stems from its ability to execute in presence of variables with non-ground values. This allows us to simulate multiple scenarios at one go. For example, several scenarios which only differ from each other in the value of a variable can be executed as a single scenario where the variable value is left uninstantiated. Similarly, we can simulate scenarios with an unbounded number of processes. We use the power of CLP(R) to also simulate charts with non-trivial timing constraints. Currently work on MSC/LSCs use symbolic variables mainly for ease of specification; they are ground during simulation. Thus, CLP technology advances the state-of-the-art in simulation and testing of MSC/LSC based requirements specifications.