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Graph Minor Approach for Application Mapping on CGRAs

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dc.contributor.author CHEN, Liang en_US
dc.contributor.author MITRA, Tulia en_US
dc.date.accessioned 2013-10-31T03:33:32Z en_US
dc.date.accessioned 2017-01-23T07:00:08Z
dc.date.available 2013-10-31T03:33:32Z en_US
dc.date.available 2017-01-23T07:00:08Z
dc.date.issued 2013-06-18 en_US
dc.identifier.uri http://hdl.handle.net/1900.100/4289 en_US
dc.description.abstract Coarse-grained reconfigurable arrays (CGRAs) exhibit high performance, improved flexibility, low cost, and power efficiency for various application domains. Computeintensive loop kernels are mapped onto CGRAs through modified modulo scheduling algorithms that integrate placement and routing. We formalize the CGRA mapping problem as a graph minor containment problem. We essentially test if the data flow graph representing the loop kernel is a minor of the modulo routing resource graph representing the CGRAs resources and their interconnects. We design an exact graph minor testing approach that exploits the unique properties of both the data flow graph and the routing resource graph to significantly prune the search space. We introduce additional heuristic strategies that drastically improve the compilation time while still generating optimal or near-optimal mapping solutions. Experimental evaluation confirms the efficiency of our approach. en_US
dc.format.extent 796598 bytes en_US
dc.format.mimetype application/pdf en_US
dc.language.iso en en_US
dc.relation.ispartofseries ;TRB6/13 en_US
dc.title Graph Minor Approach for Application Mapping on CGRAs en_US
dc.type Technical Report en_US


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